1. Field of the Invention
The present invention relates to a semiconductor package with a through silicon via (TSV) interconnect, and in particular, to an etch-stop structure for a semiconductor package with a through silicon via (TSV) interconnect.
2. Description of the Related Art
In electronic engineering, a through silicon via (TSV) is a vertical electrical connection passing completely through a silicon wafer or die. A TSV is a high performance technique, when compared to alternatives such as package-on-package, used to create three-dimensional (3D) semiconductor packages and 3D integrated circuits. The density of a TSV via is substantially higher than alternatives as the length of connections thereby are shorter.
The conventional TSV technique for forming a semiconductor package comprises forming an opening through dielectric layers of an interconnect structure and/or a semiconductor substrate of the semiconductor package. A conformal liner and a barrier seed layer are formed on sidewalls and a bottom of the opening. A conductive material such as copper (Cu), fills the opening to form a TSV. Currently, several TSV opening etching processes, comprising a via last etching process and a via middle etching process, can be selected to form TSVs. The last TSV via etching process is performed from a back side of the semiconductor substrate and is required to stop at contacts of the interconnect structure. However, poor selectivity between a semiconductor substrate (Si) and dielectric layers (Oxide) of the interconnect structure will cause a rough interface and make it difficult to control the etching profile of the TSV opening. As a result, the conductive material (Cu) filled in TSV opening will diffuse outwardly to contaminate a device.
Thus, a novel etch-stop structure for a semiconductor package with a TSV interconnect is desirable.